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Testing Of InterposerBased 25D Integrated Circuits

 
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MessagePosté le: Jeu 6 Juil - 20:05 (2017)    Sujet du message: Testing Of InterposerBased 25D Integrated Circuits Répondre en citant


Testing of Interposer-Based 2.5D Integrated Circuits
by Ran Wang



->>->>->>DOWNLOAD BOOK Testing of Interposer-Based 2.5D Integrated Circuits



This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits.  The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies.  This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable.








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